Forums Posts Latest Posts. Can you work that changes at latest bios ver 1. I can reboot, but I’d like to use hot swap. FTW3 Logo peel off. You then need to download the latest driver from this location.
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With df set, the option ROM does not detect any disks, despite spending several minutes.
Need to populate JMicron JMB362 Chip…. RESOLVED!!!
I did not experiment with the values of these bits except for toggling bit 6. The original bytes were e8 xx xxwhere e8 is the opcode for jmicon CALL instruction, and the bit immediate operand is the relative branch target. Sorry, forgot to update CRC. Option ROM not enabled by setting df, so the disks are not bootable. Stephen 1 3 9.
The sum of all bytes in the file should be 0x Thank you for this very detailed explanation. I did have some issues with the card being seated properly in the PCIe slot.
After installation is complete, Windows should ask to reboot. Final configuration PATA not enabled because turning it on causes a hang during boot.
Skiprom works best for me in hackintosh. These configuration registers seem to control the hardware directly. Header Type ‘non-bridge’ single-func Vendor: I tried modifying the option ROM to jmifron configure register 0x to this value, but had many problems booting. Any pointers would be appreciated.
Do i need to fix a checksum value as well?
Great that I can use this drive again. This seems to put the controller in AHCI mode. Duufus, I had in the past this card: I downloaded the driver for it but it installs and just disappears.
Hot-plugging the Ahc card never worked for me. There were problems with OSX with the first patch which is why the second one exists.
Forum – BIOS Modding Guides and Problems » How To – JMicron JMB AHCI mode
It is not a data table containing some form of initial register values. What am I missing here. Can someone please set me straight.
I want to create an AHCI patched verson of 1. The option ROM loads, correctly reports connected drives, and allows booting from them.
Forums Posts Latest Posts. At this point in the code, register cl should contain the byte read from PCI configuration register 0xdf.